1. HD Kallinatha, S Rai, B Talawar, A detailed study of SOT-MRAM as an alternative to DRAM primary memory in multi-core environment, IEEE Access 12, 7224-7243.
2. S Rai, B Talawar, Challenges in design, data placement, migration and power-performance trade-offs in dram-nvm-based hybrid memory systems, IETE Technical Review 40 (4), 498-520.
3. Parane, K., Prabhu Prasad, B.M., Talawar, B., LBNoc: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA, ACM Transactions on Design Automation of Electronic Systems, 2020, 25(1), 9
4. Yelmewad, P., Talawar, B., Parallel deterministic local search heuristic for minimum latency problem, Cluster Computing, 2021, 24(2), pp. 969–995
5. Prasad, B.M.P., Parane, K., Talawar, B., FPGA friendly NoC simulation acceleration framework employing the hard blocks, Computing, 2021.
6. Halavar, B., Pasupulety, U., Talawar, B., Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures, Simulation Modelling Practice and Theory, 96,101929
7. A Kumar, B Talawar, S Mahadevi, Ultra-Fast and Accurate Estimation of Large-Scale & Multi-Level Mesh-Based On-chip Architectures using Machine Learning and Multiprocessing, IEEE Access, 2026.