Simulation Approaches for Systems Verification: Simulation-Based Verification Techniques for System-Level
Designs, Simulation Types, High-Level Simulation Tools, Limitations of Simulation-Based Verification, Coverage
Metrics. Formal Verification Techniques: Equivalence Checking Combinational Equivalence Checking, Model
Checking, Semi-Formal Verification Techniques, Static Checking of Higher-Level Design Descriptions, Finite
Automata and Temporal Logic. Universal Verification Methodology (UVM): Verification Testbenches,
Analog/Mixed-Signal Verification, Use of ATPG algorithms, Programmable Hardware. Component Verification:
GPU Verification, CPU Verification, Cache Verification, SoC Verification, Challenges in Component Verifications.
New Directions in Verification: Integrated Design Validation System, Machine Learning and AI in System’s
Verification, System’s Security and Safety Verification; Increase System’s and Tools Capacity.